1. Field of the Invention
This invention relates to the field of integrated circuits, and in particular to generating the layout of such integrated circuits.
2. Description of the Prior Art
In the design of semiconductor integrated circuits, it is known to provide automated tools which use a functional design of a planned integrated circuit (for example in the form of a gate level netlist or a Register Transfer Language higher level representation of the design) and a cell library providing a set of standard cells (the standard cells being “building blocks” for putting together the layout of the integrated circuit according to the functional design) in order to generate the layout of an integrated circuit.
Typically, the standard cells are arranged in rows by the automated tool and (considering the rows as running horizontally) the left and right boundaries of each standard cell are such that any given cell may be placed next to any other given standard cell. Thus the automated tool has free choice in which standard cells are placed where in order to fulfill the requirements of the functional design with a low routing overhead.
FIG. 1A schematically illustrates a known standard cell 10, having left and right boundaries 11 and 12 respectively. Boundary regions associated with these boundaries are labelled as “A”. The dashed lines delimiting the boundary regions A from the main part of the standard cell 10 can be thought of as designating a region into which elements of the standard cell may not extend, in order to ensure that when another standard cell is placed abutting this standard cell no unwanted interactions between the elements of each standard cell will occur. In reality different elements within the standard cell (e.g. polysilicon, metal, etc.) will have different minimum distances from the boundary, according to predetermined design rules, however the boundary regions A generally illustrate a single minimum distance. When every standard cell (regardless of the particular arrangement of that standard cell) has boundaries such as those illustrated in FIG. 1A, then any standard cell may be placed abutting any other standard cell, as is schematically illustrated in FIG. 1B.
Similarly it is also known in the prior art for a standard cell to be configured such that it may only be placed in a layout in one orientation. Such a standard cell 20 is schematically illustrated in FIG. 1C. This standard cell 20 has left and right boundaries 21 and 22 respectively, which are characterized by having boundary regions A and B respectively. In this case it is necessary to place an “A” boundary next to a “B” boundary when arranging standard cells together, as is schematically illustrated in FIG. 1D. Here, standard cells 24, 25, 26 and 27 of the type illustrated in FIG. 1C are arranged in a row, such that any two standard cells meet with a “B” boundary region adjacent to an “A” boundary region. However, “A” may not be placed next to “A” and “B” may not be placed next to “B”, so it is not possible for the tool arranging the standard cells to “flip” any given cell (e.g. left-right reversing standard cell 26 in FIG. 1D), since then a “B-B” and a “A-A” abutment of standard cells would occur.
As the geometries of semiconductor integrated circuits become ever smaller, there is a growing pressure for the functionality of each standard cell to be implemented in an ever smaller area.
It would be desirable to allow this progression to ever smaller integrated circuits to continue, whilst still taking advantage of such automated tools for arranging the layout of these integrated circuits.